1. Field of the Invention
The present invention relates to the field of display technology, and in particular to an amorphous silicon semiconductor thin-film transistor (TFT) backboard structure.
2. The Related Arts
A flat panel display device has various advantages, such as thin device body, lower power consumption, and being free of radiation, and is thus widely used. The flat panel display devices that are currently available generally include liquid crystal displays (LCDs) and organic light emitting display (OLEDs).
A thin-film transistor (TFT) is an important component of a flat panel display device and can be formed on a glass substrate or a plastic substrate to generally serve as a switching device or a driving device for such as LCDs, OLEDs, or electrophoretic displays (EPDs).
According to the semiconductor material involved in a TFT, the TFTs can be classified as amorphous silicon (A-Si) semiconductor TFTs, poly-silicon (Poly-Si) semiconductor TFTs, and oxide semiconductor TFTs. Amorphous silicon is widely used in the semiconductor industry. The amorphous silicon semiconductor TFT has various advantages, such as simple manufacturing process, low cost, and being easily applicable to large-area manufacturing processes. Thus, the amorphous silicon semiconductor TFTs are most popularly used in the flat panel display devices.
Due to a relatively large potential difference existing in contact between an amorphous silicon material and a metal, it is hard for them to form an ohmic contact. In actual applications, to form an ohmic contact between a metal and an amorphous silicon semiconductor layer, it is commonplace to apply N-type heavy doping to a surface of the semiconductor layer that is in contact with the metal, namely doping a high concentration of phosphor (P) element in the surface of the semiconductor layer that is in contact with the metal in order to lower the contact resistance between the metal layer and the semiconductor layer.
FIG. 1 shows a conventional amorphous silicon semiconductor TFT backboard structure, which comprises a base plate 10, a gate electrode 20, a gate insulation layer 30, an amorphous silicon semiconductor layer 40, a source electrode 60, and a drain electrode 70. The amorphous silicon semiconductor layer 40 has a dual-layered structure, of which a bottom layer that is in contact with the gate insulation layer 30 is a pure amorphous silicon layer 41 without being subjected to any treatment and a top layer that is in contact with the source electrode 60 and the drain electrode 70 is an N-type heavily-doped amorphous silicon layer 42. The N-type heavily-doped amorphous layer 42 forms ohmic contact with the source electrode 60 and the drain electrode 70 so as to reduce the contact resistance between the source and drain electrodes 60, 70 and the semiconductor layer 40, thereby heightening current efficiency and increasing ON-state current (Ion).
However, the amorphous silicon semiconductor TFT backboard structure shown in FIG. 1 suffers certain problems while increasing the ON-state current. As indicated by a TFT current curve illustrated with phantom lines in FIG. 3, when a gate voltage (Vg) of a TFT is a negative voltage and the negative voltage is increased to a predetermined level, more positive charges will be excited and generated to form a hole conduction channel, leading to a relatively large hole current (Ioff), so as to reduce the reliability of the TFT and making electrical stability of the TFT deteriorating.